JPH0317252B2 - - Google Patents
Info
- Publication number
- JPH0317252B2 JPH0317252B2 JP58018755A JP1875583A JPH0317252B2 JP H0317252 B2 JPH0317252 B2 JP H0317252B2 JP 58018755 A JP58018755 A JP 58018755A JP 1875583 A JP1875583 A JP 1875583A JP H0317252 B2 JPH0317252 B2 JP H0317252B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- output
- oscillator
- oscillation
- programmable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000010355 oscillation Effects 0.000 claims description 49
- 238000006243 chemical reaction Methods 0.000 claims description 15
- 238000013459 approach Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/185—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using a mixer in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58018755A JPS59146228A (ja) | 1983-02-09 | 1983-02-09 | Pll周波数シンセサイザ |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58018755A JPS59146228A (ja) | 1983-02-09 | 1983-02-09 | Pll周波数シンセサイザ |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59146228A JPS59146228A (ja) | 1984-08-22 |
JPH0317252B2 true JPH0317252B2 (en]) | 1991-03-07 |
Family
ID=11980458
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58018755A Granted JPS59146228A (ja) | 1983-02-09 | 1983-02-09 | Pll周波数シンセサイザ |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59146228A (en]) |
-
1983
- 1983-02-09 JP JP58018755A patent/JPS59146228A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS59146228A (ja) | 1984-08-22 |
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